电子设计自动化工具

SynaptiCAD was founded by electrical engineers to create design tools that helped engineers think critically about their designs. Being engineers themselves, they were frustrated by having to almost complete a design before being able to get simulation results. Our founders decided that there must be a better approach for interacting with design tools and from this simple idea they created SynaptiCAD, a company that creates “tools for the thinking mind”. This idea permeates all of our tool interfaces. With SynaptiCAD’s tools you are able to begin analyzing and simulating design ideas right away without having to complete an entire circuit model or schematic. Our tools automatically handle many of the minor details involved in the design effort, leaving you more time to focus on the bigger picture.

Family of products from SynaptiCAD. The software package developed by SynaptiCAD for the analysis of the schemes. Includes 8 programs for finite element analysis of electronic projects: TestBencher Pro, VeriLogger Pro, WaveFormer Pro, WaveFormer Lite, DataSheet Pro, Timing Diagrammer Pro, BugHunter, Gigawave Viewer. In this system synthesis test performs program TestBencher Pro, which generates the HDL-code for the bus synchronous and asynchronous transactions on time charts, drawn up by the user. SynaptiCAD is a multilevel system, as can work together with modeling programs at the levels of RTL, the barrier and the transistor.

Modern integrated CAD VLSI consist of a large number of programs that differ in the orientation of the various design procedures and different types of schemes. The best-known creators of integrated CAD companies are Mentor Graphics, Cadence Design Systems, Synopsys. In addition to these individual programs or group of programs offered by many firms operating in the area of ECAD. One of the known systems of synthesis of tests is SynaptiCAD company Simucad. In this system synthesis test performs program TestBencher Pro, which generates the HDL-code for the bus synchronous and asynchronous transactions on time charts, drawn up by the user. The user can adjust the time diagrams, and TestBencher Pro them quickly studied. Modeling bus transaction is accompanied by fixation of unexpected values of signals and transactions.

Functional Modeling (Functional Simulation) allows you to check the correctness of the scheme. For these purposes, the package Libero is used widely known product ModelSim. In addition, for the generation of test actions used product WaveFormer Lite Company SynaptiCAD. Tracing the project to the selected user FPGA by using its own product Designer, who also has a tool for analyzing the temporal characteristics of Designer’s Timer tool, allowing a static analysis of delay of signals on a chip; means placing macros ChipEdit; means the appointment of contacts PinEdit. After placement and routing of the project on a chip using a package of ModelSim executed temporal modeling (timing simulation).

SynaptiCAD 公司出品的 EDA（电子设计自动化）工具集合，包括HDL输入、仿真、测试、波形分析、管脚映射工具等等,是一个很完整的EDA方案。

SynaptiCAD Product Suite 由电机工程师创造设计的一款电子互动设计工具，这个互动概念贯穿于所有的接口。您可以开始分析和模拟设计理念，毋须经完成整个电路模型或示意图，帮助工程师他们的设计进行批判性的审视。

SynaptiCAD Product Suite 包含了9种功能强大的工具：
1.TestBencher Pro：
用于从独立于语言的时序逻辑表生成交互式VHDL,Verilog, OpenVera,e, 和TestBuilder 测试基准及总线功能的模型。生成的测试基准能提供基于仿真相应的不同的激发向量，以便于测试基准功能作为一个被测试系统环境的动作模型正常工作。 TestBencher Pro是一个优秀的测试大规模FPGA 和 ASIC设计的工具。
2.BugHunter Pro：
一款用于 Verilog， VHDL 和 C++ 模拟器的图形调试系统。BugHunter 支持所有主要的 HDL 模拟器，其主要功能包括：单一步骤调试、波形数据串流、项目管理等等。可以侦测程序与帮助系统的交互过程从而发现问题所在。
3.VeriLogger Pro：
Verilog模拟器软件。提供一个综合了传统Verilog模拟器所有特征的仿真环境，它具有强大的图形测试矢量产生器。VeriLogger的快速模型测试使用户可以对设计中的每个模型进行“自底向上”的测试。
4.WaveFormer Pro：
由时序图分析器、模拟器和测试向量生成器组合而成。它为设计人员提供了一个集成的环境，可以用来开发数字和模拟线路的时序图。WaveFormer Pro可以由Spice模拟器，Mathematica，或Matlab等工具输入模拟数据。还可以利用WaveFormer Pro 内部拥有的波形函数直接生成模拟信号；或者将从总线上得到的数字信号变换成模拟信号。还可以将模拟信号波形逐段线性地变换成Spice模拟器的电压信号源。
5.SimuTAG：
一款功能强大和实时地查证出 FPGAs 的错误的系统。可经由比较FPGA 功能规则反证RTL样式模拟规则，迅速发现逻辑和综合错误。
6.PinPort：
提供数字硬件与Verilog 或C++的虚拟接口环境。
7.DataSheet Pro：
时间表文件夹管理工具。
8.Timing Diagrammer Pro：
时间表设计工具。
9.Gigawave Viewer：
波形观测器。

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